Education Profile

  • M. Tech in Very Large-Scale Integration, Indian Institute of Technology (IIT), Mandi, India, 2021 
  • B.Tech in Electronics System Engineering, National Institute of Electronics and Information Technology, Aurangabad, Maharashtra, India, 2018

Office location

  • Building 5 Sea-side, Level 2, Office 2206-WS09.

Work Experience

  • Visiting Student, Innovative Technologies Laboratories, KAUST, Saudi Arabia
    Guide: Dr. Yehia Massoud, Professor, ITL, KAUST (Dec 2021- Aug 2022)
  • Graduate Teaching Assistant, IIT Delhi
    Guide: Dr. Rahul Mishra, Assistant Professor, CARE, IIT Delhi (Aug 2021- Oct 2021)
  • Visiting Student, Integrated Circuits and System Group, KAUST, Saudi Arabia
    Guide: Dr. Hossein Fariborzi, Assistant Professor, ICS, KAUST (June 2021- Aug 2021)
  • Graduate Teaching Assistant, IIT Mandi
    Guide: Dr. Srikant Srinivasan, Associate Professor, SCEE, IIT Mandi (Aug 2019- June 2021)

Honors and Awards

  • MHRD Fellowship (GATE), Govt. Of India, 2019
  • Bidhan-Lokmanya Scholarship, Indian Railways, Govt. Of India, 2014


Divyanshu is a Ph.D. student in the Innovative Technologies Laboratories (ITL) under the supervision of Professor Yehia Massoud at King Abdullah University of Science and Technology (KAUST).

Research Interests

His research interest lies in the spintronic device application in hardware security, from device level simulation to circuit designing.


  1. D. Divyanshu, R. Kumar, D. Khan, S. Amara and Y. Massoud, “FSM inspired unconventional Hardware Watermark using field-assisted SOT-MTJ,” IEEE Access, 2023.
  2. D. Divyanshu, R. Kumar, D. Khan, S. Amara and Y. Massoud, “An Approach towards Designing Logic Locking Using Shape-Perpendicular Magnetic Anisotropy-Double Layer MTJ,” Electronics, 2023.
  3. D. Divyanshu, R. Kumar, D. Khan, S. Amara and Y. Massoud, “Finite-State-Machine Inspired Hardware Watermark Using Spin-Orbit Torque Operated MTJ,” 56th IEEE International Symposium on Circuits and Systems (ISCAS), California, USA, May. 2023. (Accepted)
  4. R. Kumar, D. Divyanshu, D. Khan, S. Amara and Y. Massoud, “Modelling of sneaky Hardware Trojan using SOT assisted MTJ for high-speed digital circuits,” 18th IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), China, Nov. 2022. (Accepted)
  5. A. Lone, D. Divyanshu, S. Amara, and H. Fariborzi, “Voltage Controlled Static Skyrmion Device for Neuromorphic Computing Applications", Special MRAM poster session, IEDM 2021. (Poster)