Improving chip design on every level

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A programming framework could streamline chip design by bridging the gap between conceptual design and practical execution. This may help address the ongoing challenge in the computer hardware industry of meeting the demand for high-performance, energy-efficient electronic devices at ever smaller scales.

This demand has long posed a challenge: it requires not only smaller transistors and microchips but also innovative new hardware architectures that provide the optimum arrangements of components for rapid data flow and processing. However, transforming a high-level design — exactly what we want a chip to do — into the low-level details of practical hardware is a lengthy, complex process requiring multiple iterations and collaboration across multiple teams.

In developing the framework, called Assassyn (ASynchronous Semantics for Architectural Simulation and SYNthesis), researchers—including Jian Weng from KAUST—incorporated both architectural simulation and real-world hardware implementation.

Read the full story on KAUST Discovery.