Developing, Synthesizing, and Automating Domain-Specific Accelerators

Overview

Abstract

In reaction to the waning benefit of transistor scaling and the increasing demands on computing power, specialized accelerators have drawn significant attention from both academics and industry because of their orders-of-magnitude performance improvement and energy efficiency. All these accelerators require intensive engineering efforts, from designing the architecture to having a full-stack implementation. Therefore, the software/hardware co-designed innovations are often monopolized by several large teams in large companies. In this talk, I will first discuss how my research democratizes the accelerator designs and unifies the hardware/software innovations by automating the accelerator design paradigm under a unified programming interface. By taking advantage of the compiler’s awareness of the program behaviors that profit from hardware specialization, accelerators can be automatically synthesized by searching through a well-defined design space. These automatically designed accelerators achieve comparable cost/performance efficiency compared with prior handcrafted designs. In the rest of the talk, I will cover how this work inspires me to apply the principles to applicable questions, including compiling emerging instruction paradigms developed by hardware vendors, and how I take advantage of the generated accelerators to reform the existing FPGA programming paradigm. I will also discuss some future directions of my research.

Brief Biography

Jian Weng earned his PhD degree from UCLA in September of 2023 under the guidance of Professor Tony Nowatzki. His research interests span specialized accelerator design, analysis, and implementation, as well as their associated software stacks. His works have been accepted by top-tier architecture conferences, including CGO, HPCA, ISCA, and MICRO. He has one work selected as IEEE Micro Honorable Mentions and one work awarded as MICRO best paper runner up.