Leo Raj Solay

About

Leo Raj Solay joined as a Ph.D. candidate in the Advanced Semiconductor Laboratory (ASL) group of the Computer Electrical and Mathematical Sciences & Engineering (CEMSE) division at King Abdullah University of Science and Technology (KAUST) in August 2023. Post Graduated with a Master of Technology (M. Tech.) degree in Very Large Scale Integration (VLSI) from Amity University Uttar Pradesh, Noida, India in 2019. Graduated with a Bachelor of Technology (B. Tech.) degree in Electronics and Communication Engineering (ECE) from Jawaharlal Nehru Technological University, Hyderabad, India in 2016. 

His research focussed on the design of Nanowire Field Effect Transistors (NW-FETs) and their performance analysis. He worked on simulation-based device performance enhancement techniques such as Gate Engineering (Dual Material and Triple Material Gates), Gate Dielectric Stacking (SiO2+High-k dielectrics), Ferroelectric Negative Capacitance technique, and sensitivity analysis of Biosensor device applications.

He published his 5 research works in SCI-indexed peer-reviewed journals as the first and corresponding author and co-authored 4 peer-reviewed journal publications. 

RESEARCH INTERESTS

Leo’s research interests incline to Wide Band Gap (WBG) and Ultra Wide Band Gap (UWBG) semiconductors device-based research, their fabrication, characterization, and applications for future nanotechnology.