Spatial Dataflow is all you need!

Overview

Transistor scaling not only offers more and more on-chip resources to improve the chip performance, but also urges system developers to design and implement better computer architectures to better utilize these resources. However, existing architectural design and implementation approaches still rely on separate codebases for both simulation-based design decision modeling, and RTL implementation. Jian Weng’s research view these technical challenges in a view of spatial dataflow, and proposes a brand-new abstraction for unified design and implementation. By taking advantage of a widely existing programming paradigm in software engineering, a concise, expressive, and efficient hardware design and implementation framework is proposed. This approach achieves near handcraft performances, while saving 64% LoC. Moreover, Jian Weng is going to apply the spatial dataflow methodology on a next-generation ML inference system by taking advantage of the larger and larger on-chip memory to amortize the memory bottleneck.