High-Mobility Back-End-of-Line Compatible Indium Oxide Thin-Film Transistors for Monolithic 3D Integration

Overview

The continuous scaling of silicon complementary metal-oxide semiconductor (CMOS) transistors has driven significant technological advancements, enabling denser, faster, and more cost-effective integrated circuits. However, as technology nodes shrink below 10 nm, further progress in three-dimensional (3D) scaling of transistors faces substantial challenges, including increased process complexity and additional manufacturing steps. Additionally, the concurrent scaling of interconnects exacerbates parasitic resistance and capacitance, leading to reduced signal bandwidth and increased power consumption. To overcome these limitations, three-dimensional (3D) integration technology has emerged as a promising alternative.

Monolithic 3D integration (M3DI), which involves fabricating transistors in the back-end-of-line (BEOL), offers unique advantages, including cost-effective processes and ultrahigh-density interconnecting-vias (>10⁷/mm²). However, fabricating high-performance BEOL-compatible transistors within a strict thermal budget (<400 °C) remains a critical challenge. Oxide semiconductors (OSs) have emerged as promising materials for BEOL-compatible transistors due to their high mobility, extremely low leakage current, low-temperature processing capabilities, and large-area scalability.

This dissertation explores strategies for developing high-mobility BEOL-compatible indium oxide (In₂O₃) thin-film transistors (TFTs) for M3DI. First, a BEOL-compatible process was established to achieve high field-effect mobility (μFE >40 cm²V⁻¹s⁻¹) In₂O₃ TFTs through a straightforward post-annealing method. The influence of annealing on the electrical performance of sputtered In₂O₃ TFTs was studied, with a focus on changes in oxygen-related species in the In₂O₃ channel.

Next, a novel approach combining a sputtered Al₂O₃ passivation layer with O2 plasma pretreatment was developed to enhance mobility and stability of In₂O₃ TFTs. This method resulted in devices with a record-high μFE of 128.3 cm²V⁻¹s⁻¹ at a low thermal budget of 200°C, along with excellent bias stability among passivated OS TFTs.

Furthermore, enhancement-mode In₂O₃ TFTs with recessed-channel structures were demonstrated using a dry etching process for precise channel thickness engineering. These devices exhibited a high µFE of 55.6 cm²V⁻¹s⁻¹ at an overall process temperature of 200 °C, establishing a new benchmark for sputtered OS TFTs.

Lastly, temperature-dependent electron transport in In₂O₃ TFTs was analyzed down to a cryogenic temperature of 2K. Benchmarking revealed that the developed BEOL-compatible In₂O₃ TFTs achieved the highest µFE of 43 cm²V⁻¹s⁻¹ at cryogenic temperatures among all reported OS TFTs.