Accelerated, Connected, Efficient: Revisiting Computing Abstractions, from Bit to Network

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B2/3 A0215

This talk examines the hidden cost of the abstractions computing is built on, and how the Accelerated Connected Computing Lab at KAUST has revisited them, from arithmetic and dataflow architectures to network-attached accelerators.

Producing a single word from a modern AI model takes orders of magnitude more energy than the arithmetic that underpins it. The rest goes to the abstractions computing has been built on: how numbers are represented, how data moves through memory and processors, and how accelerators are attached to servers and networks. Transistor scaling once hid these costs but no longer does.  As AI moves into constrained, private, and sovereign settings these abstractions become the limiting factor. In this talk, the work of the Accelerated Connected Computing Lab on revisiting these abstractions at three levels will be presented. First, network-attached FPGA accelerators that serve requests directly, without a host server, using reconfiguration guided by what the application needs. Second, compilation approaches that map computation efficiently onto spatial dataflow architectures, including commercial AI engines and heterogeneous coarse-grained arrays. Third, arithmetic designed around the accuracy applications need, using emerging block-scaled number formats and how operators are composed at the architecture level. The presentation will close with how this cross-stack expertise has lays a foundation for future accelerator design in the Kingdom.

Presenters

Brief Biography

Suhaib Fahmy is Associate Professor of Computer Science and the principal investigator of the KAUST Accelerated Connected Computing Laboratory (ACCL).

Professor Fahmy graduated from Imperial College London with an M.Eng. in Information Systems Engineering in 2003 and a Ph.D. in Electrical and Electronic Engineering in 2008. Following his Ph.D., he joined Trinity College Dublin, Ireland, as a postdoctoral research fellow and later worked as a visiting research engineer at Xilinx Research Labs Ireland, focusing on reconfigurable computing systems.

He was Assistant Professor of Computer Engineering at Nanyang Technological University, Singapore from 2009–2015, where his team led early efforts to virtualize FPGAs for cloud computing, as well as pioneering work on efficient mapping of designs to FPGA primitives.

In 2015, he returned to the UK, joining the University of Warwick Associate professor, Reader, the Professor of Computer Engineering. While at Warwick, he led the Connected Systems Research Group and the Adaptive Reconfigurable Computing Lab and launched the joint Computer Systems Engineering degree program. He was also appointed a Turing Fellow at The Alan Turing Institute, the UK’s national institute for data science and artificial intelligence.

He has received numerous awards, including the IEEE Conference on Field Programmable Technology (FPT) Best Paper Award in 2012, IBM Faculty Awards in 2013 and 2017, the International Conference on Field-Programmable Logic and Applications (FPL) Community Award in 2016 and 2024, the ACM Transactions on Design Automation of Electronic Systems Best Paper Award in 2019, and the IEEE High Performance Extreme Computing Conference Best Paper Award in 2021.

In 2023, he was awarded the KAUST Distinguished Teaching Award for his exceptional contributions to the classroom instruction mission of the University.

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