Exploring FPGAs for Virtualized In-Network Acceleration

Overview

Abstract

With increasing connectivity and reliance on machine intelligence to process ever-growing amounts of data, the question of how to arrange the required connectivity and computation arises. Traditional cloud computing approaches that centralize compute capability in a data center do not scale well to large scale distributed data sources that must then transmit data over constrained networks. Similarly, computing at the very edge of the network is often constrained by limited computational capacity and a lack of access to shared data. In-network computing has been proposed as a way of moving some computational load into the network, potentially taking advantage of extra compute capacity in programmable network switches. Another approach could be the use of FPGAs that are capable of performing network functions and also supporting application accelerators. We will explore the present use of FPGAs to accelerate applications in traditional datacenters before investigating the latency limits resulting from such deployments for streaming applications. We will then propose how existing work on virtualizing FPGA accelerators could be adapted for an in-network computing approach. We will present some results on experiments that explore the space between the cloud and edge and raise topics of interest for research into this emerging area.

Brief Biography

Suhaib Fahmy is Reader (Associate Professor) in Computer Engineering at the University of Warwick, where he leads the Connected Systems Research Group and Adaptive Reconfigurable Computing Lab. He is also a Turing Fellow at The Alan Turing Institute in London. He graduated with MEng and Ph.D. degrees from Imperial College London in 2003 and 2008, respectively. After a postdoc at Trinity College Dublin in a collaboration with Xilinx Research Labs, Ireland, he moved to Nanyang Technological University Singapore in 2009, returning to the UK in 2015. His research explores the use of reconfigurable architectures for accelerating complex computations and tighter coupling of computation and communication in embedded and larger networks. He received the Best Paper Award at the IEEE Conference on Field-Programmable Technology (FPT) in 2012, an IBM Faculty Award in 2013 and 2017, the Community Award at the International Conference on Field-Programmable Logic and Applications (FPL) in 2016, and the ACM Transactions on Design Automation of Electronic Systems Best Paper Award in 2019. He serves widely on technical program committees in the area of reconfigurable computing and has been technical program chair for ASAP, HEART, FPL, and topic chair for DATE. He sits on the ACM Technical Committee on FPGAs and Reconfigurable Computing. Dr. Fahmy is a Senior Member of the IEEE, Senior Member of the ACM, Chartered Engineer and Member of the IET, and Fellow of the Higher Education Academy.