Kartci, Aslihan, et al. "CMOS-RC Colpitts oscillator design using floating fractional-order inductance simulator." IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2018, 905.
This paper deals with CMOS fractional-order inductance (FoL) simulator design and its utilization in 2.75 th order Colpitts oscillator providing high frequency of oscillation. The proposed floating FoL is composed of two unity-gain current followers (CF±s), two inverting voltage buffers, a transconductor, and a fractional-order capacitor (FoC) of order 0.75, while the input intrinsic resistance of CF± is used as design parameter instead of passive resistor. The resulting equivalent inductance value of the FoL can be adjusted via order of FoC, which was emulated via 5 th -order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 kHz - 2.45 MHz the L y shows ±5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 μm level-7 LO EPI SCN018 CMOS process parameters with ±1 V supply voltages.