Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77 Gbitss

Fig. 2. Oscilloscope trace of the output time waveforms of the X variable illustrating controllable operation of (a) System 1, (b) System 2, (c) System 3 and (d) System 4. The output waveform of X is shown in yellow and the control parameter M is shown in blue. The results are experimental output from the physical FPGA in real-time. (For interpretation of the references to color in this figure caption, the reader is referred to the web version of this paper.)

Abhinav S. Mansingka,  Mohammed Affan Zidan,  Mohamed L. Barakat, Ahmed G. Radwan, Khaled N. Salama. 

Microelectronics Journal Volume 44, Issue 9, September 2013, Pages 744-752 

Abstract: This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100× higher maximum Lyapunov exponent than the original jerk-equation based chaotic systems. The resulting chaotic output is shown to pass the NIST SP. 800-22 statistical test suite for pseudo-random number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators.