Designing, Synthesizing, and Automating Domain-Specific Accelerators

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In reaction to the waning benefit of transistor scaling and the increasing demands on computing power, specialized accelerators have drawn significant attention from both academics and industry because of their orders-of-magnitude performance improvement and energy efficiency. All these accelerators require non-trivial human efforts, from designing the architecture to having a full-stack implementation. Therefore, the software/hardware co-designed innovations are often monopolized by several large teams in large companies. In this talk, I will first discuss how my research democratizes the accelerator designs and unifies the hardware/software innovations by automating the accelerator design process under a unified programming paradigm. By taking advantage of the compiler’s awareness of the program behaviors that profit from hardware specialization, accelerators can be automatically synthesized by searching through a well-defined design space. These automatically designed accelerators achieve comparable cost/performance efficiency compared with prior handcrafted designs. In the rest of the talk, I will also cover how this work inspires me to develop techniques to accelerate emerging application domains by orders-of-magnitude speedup, including digital signal processing and DNN inference, and how I take advantage of this work to revolutionize the FPGA programming paradigm.

Brief Biography

Jian Weng is a 6th-year PhD student from UCLA advised by Tony Nowatzki. His research interests span specialized accelerator design, and their associated compiling techniques. His works have been accepted by top-tier architecture conferences. He has one work selected as IEEE Micro Honorable Mentions and one work awarded as MICRO best paper runner-up.

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